AMCG1IDR_EL0

This register is present only when FEAT_AMUv1p1 is implemented. Otherwise, direct accesses to AMCG1IDR_EL0 are UNDEFINED.

Attributes

Field descriptions

Bits [63:32]:

AMEVCNTOFF1<n>_EL2, bit [n+16], for n = 15 to 0:

Indicates which implemented auxiliary counters have a corresponding virtual offset register, AMEVCNTVOFF1<n>_EL2 implemented.

AMEVCNTOFF1<n>_EL2	Meaning
0b0	AMEVCNTR1<n>_EL0 does not have an offset, or is not implemented.
0b1	The offset AMEVCNTVOFF1<n>_EL2 is implemented for AMEVCNTR1<n>_EL0.

AMEVCNTR1<n>_EL0, bit [n], for n = 15 to 0:

Indicates which auxiliary counters AMEVCNTR1<n>_EL0 are implemented.

AMEVCNTR1<n>_EL0	Meaning
0b0	AMEVCNTR1<n>_EL0 is not implemented.
0b1	AMEVCNTR1<n>_EL0 is implemented.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, AMCG1IDR_EL0

(op0 = 0b11, op1 = 0b011, CRn = 0b1101, CRm = 0b0010, op2 = 0b110)

if !IsFeatureImplemented(FEAT_AMUv1p1) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && CPTR_EL3().TAM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if AMUSERENR_EL0().EN == '0' then AArch64_SystemAccessTraptoEL1orEL2(0x18); elsif EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCG1IDR_EL0(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && CPTR_EL2().TAM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCG1IDR_EL0(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && CPTR_EL3().TAM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = AMCG1IDR_EL0(); end; elsif PSTATE.EL == EL3 then X{64}(t) = AMCG1IDR_EL0(); end;