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AMCG1IDR_EL0

Activity Monitors Counter Group 1 Identification Register

Defines which auxiliary counters are implemented, and which of them have a corresponding virtual offset register, AMEVCNTVOFF1<n>_EL2 implemented.

Configuration

This register is present only when FEAT_AMUv1p1 is implemented. Otherwise, direct accesses to AMCG1IDR_EL0 are UNDEFINED.

Attributes

AMCG1IDR_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
AMEVCNTOFF115_EL2AMEVCNTOFF114_EL2AMEVCNTOFF113_EL2AMEVCNTOFF112_EL2AMEVCNTOFF111_EL2AMEVCNTOFF110_EL2AMEVCNTOFF19_EL2AMEVCNTOFF18_EL2AMEVCNTOFF17_EL2AMEVCNTOFF16_EL2AMEVCNTOFF15_EL2AMEVCNTOFF14_EL2AMEVCNTOFF13_EL2AMEVCNTOFF12_EL2AMEVCNTOFF11_EL2AMEVCNTOFF10_EL2AMEVCNTR115_EL0AMEVCNTR114_EL0AMEVCNTR113_EL0AMEVCNTR112_EL0AMEVCNTR111_EL0AMEVCNTR110_EL0AMEVCNTR19_EL0AMEVCNTR18_EL0AMEVCNTR17_EL0AMEVCNTR16_EL0AMEVCNTR15_EL0AMEVCNTR14_EL0AMEVCNTR13_EL0AMEVCNTR12_EL0AMEVCNTR11_EL0AMEVCNTR10_EL0

Bits [63:32]:

Reserved, RES0.

AMEVCNTOFF1<n>_EL2, bit [n+16], for n = 15 to 0:

Indicates which implemented auxiliary counters have a corresponding virtual offset register, AMEVCNTVOFF1<n>_EL2 implemented.

AMEVCNTOFF1<n>_EL2Meaning
0b0

AMEVCNTR1<n>_EL0 does not have an offset, or is not implemented.

0b1

The offset AMEVCNTVOFF1<n>_EL2 is implemented for AMEVCNTR1<n>_EL0.

AMEVCNTR1<n>_EL0, bit [n], for n = 15 to 0:

Indicates which auxiliary counters AMEVCNTR1<n>_EL0 are implemented.

AMEVCNTR1<n>_EL0Meaning
0b0

AMEVCNTR1<n>_EL0 is not implemented.

0b1

AMEVCNTR1<n>_EL0 is implemented.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, AMCG1IDR_EL0

(op0 = 0b11, op1 = 0b011, CRn = 0b1101, CRm = 0b0010, op2 = 0b110)

if !IsFeatureImplemented(FEAT_AMUv1p1) then UNDEFINED; elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif AMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = AMCG1IDR_EL0; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif EL2Enabled() && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = AMCG1IDR_EL0; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = AMCG1IDR_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = AMCG1IDR_EL0;

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