Extended Auxiliary Memory Attribute Indirection Register (EL3)
Provides IMPLEMENTATION DEFINED memory attributes for the memory regions specified by MAIR2_EL3.
This register is present only when FEAT_AIE is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to AMAIR2_EL3 are UNDEFINED.
AMAIR2_EL3 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
| IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED.
Accesses to this register use the following encodings in the System register encoding space:
MRS <Xt>, AMAIR2_EL3
(op0 = 0b11, op1 = 0b110, CRn = 0b1010, CRm = 0b0011, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_AIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = AMAIR2_EL3(); end;
MSR AMAIR2_EL3, <Xt>
(op0 = 0b11, op1 = 0b110, CRn = 0b1010, CRm = 0b0011, op2 = 0b001)
if !(IsFeatureImplemented(FEAT_AIE) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3().AMAIR2_EL3 == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else AMAIR2_EL3() = X{64}(t); end; end;
Version 2026.06 — Copyright © 2010-2026 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.