If EL2 is implemented, invalidate all cached copies of translation table entries from TLBs that meet the following requirements:
The invalidation is not required to apply to caching structures that combine stage 1 and stage 2 translation table entries.
The invalidation only applies to the PE that executes this System instruction.
This instruction is present only when FEAT_AA32EL2 is implemented. Otherwise, direct accesses to TLBIIPAS2 are UNDEFINED.
This System instruction is not implemented in architecture versions before Armv8.
TLBIIPAS2 is a 32-bit System instruction.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | IPA[39:12] | ||||||||||||||||||||||||||||||
Reserved, RES0.
Bits[39:12] of the intermediate physical address to match.
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
Accesses to this instruction use the following encodings in the System instruction encoding space:
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b100 | 0b1000 | 0b0100 | 0b001 |
if !IsFeatureImplemented(FEAT_AA32EL2) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T8 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then AArch32.TLBI_IPAS2(SecurityStateAtEL(EL1), Regime_EL10, VMID[], Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, R[t]); elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then UNDEFINED; elsif SCR.NS == '0' then return; else AArch32.TLBI_IPAS2(SS_NonSecure, Regime_EL10, VMID_NONE, Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, R[t]);