Secure Debug Enable Register
Controls invasive and non-invasive debug in the Secure EL0 mode.
AArch32 System register SDER bits [31:0] are architecturally mapped to AArch64 System register SDER32_EL2[31:0] when EL2 is implemented and FEAT_SEL2 is implemented.
AArch32 System register SDER bits [31:0] are architecturally mapped to AArch64 System register SDER32_EL3[31:0] when EL3 is implemented.
This register is present only when (EL3 is implemented and FEAT_AA32EL3 is implemented) or (FEAT_AA32EL1 is implemented and Secure EL1 is implemented). Otherwise, direct accesses to SDER are UNDEFINED.
SDER is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | SUNIDEN | SUIDEN | |||||||||||||||||||||||||||||
Reserved, RES0.
Secure User Non-Invasive Debug Enable.
| SUNIDEN | Meaning |
|---|---|
| 0b0 |
This bit has no effect on non-invasive debug. |
| 0b1 |
Non-invasive debug is allowed in Secure EL0 using AArch32. |
When EL3 or Secure EL1 is using AArch32, the forms of non-invasive debug affected by this control are:
When Secure EL1 is using AArch64, this bit has no effect.
The reset behavior of this field is:
Secure User Invasive Debug Enable.
| SUIDEN | Meaning |
|---|---|
| 0b0 |
This bit does not affect the generation of debug exceptions at Secure EL0. |
| 0b1 |
If EL3 or EL1 is using AArch32, debug exceptions from Secure EL0 are enabled. |
The reset behavior of this field is:
Reserved, RES0.
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b0001, CRm = 0b0001, opc2 = 0b001)
if !((HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3)) || (IsFeatureImplemented(FEAT_AA32EL1) && HaveELUsingSecurityState(EL1, TRUE))) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif !IsCurrentSecurityState(SS_Secure) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = SDER; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then R[t] = SDER;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b0001, CRm = 0b0001, opc2 = 0b001)
if !((HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3)) || (IsFeatureImplemented(FEAT_AA32EL1) && HaveELUsingSecurityState(EL1, TRUE))) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif !IsCurrentSecurityState(SS_Secure) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then AArch64.AArch32SystemAccessTrap(EL3, 0x03); else SDER = R[t]; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if CP15SDISABLE2 == HIGH then UNDEFINED; else SDER = R[t];
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