Performance Monitors Software Increment register
Increments a counter that is configured to count the Software increment event, event 0x00. For more information, see 'SW_INCR'.
AArch32 System register PMSWINC bits [31:0] are architecturally mapped to AArch64 System register PMSWINC_EL0[31:0].
AArch32 System register PMSWINC bits [31:0] are architecturally mapped to External register PMSWINC_EL0[31:0] when FEAT_PMUv3p9 is not implemented.
This register is present only when FEAT_AA32 is implemented and FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMSWINC are UNDEFINED.
PMSWINC is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
Reserved, RES0.
Software increment.
| P<m> | Meaning |
|---|---|
| 0b0 |
Write is ignored. |
| 0b1 |
Increment PMEVCNTR<m>, if PMEVCNTR<m> is configured to count software increment events. |
Accessing this field has the following behavior:
Accesses to this register use the following encodings in the System register encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b1001, CRm = 0b1100, opc2 = 0b100)
if !(IsFeatureImplemented(FEAT_AA32) && IsFeatureImplemented(FEAT_PMUv3)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL != EL3 && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then Undefined(); elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && ((IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().[UEN,SW,EN] == '000') || (!IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0().[SW,EN] == '00')) then AArch64_AArch32SystemAccessTraptoEL1orEL2(0x03); elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && PMUSERENR().[SW,EN] == '00' then if EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && HCR_EL2().TGE == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HCR().TGE == '1' then AArch32_TakeHypTrapException(0x00); else Undefined(); end; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && EffectivelyAtEL0NotInHost() && HSTR_EL2().T9 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HSTR().T9 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1)) && EffectivelyAtEL0NotInHost() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMSWINC_EL0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && MDCR_EL2().TPM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HDCR().TPM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; else PMSWINC() = R(t); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T9 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T9 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2().TPM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR().TPM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; else PMSWINC() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; else PMSWINC() = R(t); end; elsif PSTATE.EL == EL3 then PMSWINC() = R(t); end;
Version 2026.06 — Copyright © 2010-2026 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.