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MAIR1: Memory Attribute Indirection Register 1

Purpose

Along with MAIR0, provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.

AttrIndx[2] indicates the MAIR register to be used:

Configuration

This register is banked between MAIR1 and MAIR1_S and MAIR1_NS.

AArch32 System register MAIR1 bits [31:0] are architecturally mapped to AArch64 System register MAIR_EL1[63:32] when EL3 is not implemented or EL3 is using AArch64.

AArch32 System register MAIR1 bits [31:0] are architecturally mapped to AArch32 System register NMRR[31:0] when EL3 is not implemented or EL3 is using AArch64.

AArch32 System register MAIR1 bits [31:0] (MAIR1_NS) are architecturally mapped to AArch32 System register NMRR[31:0] (NMRR_NS) when EL3 is using AArch32.

AArch32 System register MAIR1 bits [31:0] (MAIR1_S) are architecturally mapped to AArch32 System register NMRR[31:0] (NMRR_S) when EL3 is using AArch32.

This register is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to MAIR1 are UNDEFINED.

MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE:

When EL3 is using AArch32, write access to MAIR1(S) is disabled when the CP15SDISABLE signal is asserted HIGH.

Attributes

MAIR1 is a 32-bit register.

This register has the following instances:

Field descriptions

When TTBCR.EAE == 1:

313029282726252423222120191817161514131211109876543210
Attr7Attr6Attr5Attr4

Attr<n>, bits [8(n-4)+7:8(n-4)], for n = 7 to 4

The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:

Bits [7:4] are encoded as follows:

Attr<n>[7:4]Meaning
0b0000Device memory. See encoding of Attr<n>[3:0] for the type of Device memory.
0b00RW, RW not 0b00Normal memory, Outer Write-Through Transient.
0b0100Normal memory, Outer Non-cacheable.
0b01RW, RW not 0b00Normal memory, Outer Write-Back Transient.
0b10RWNormal memory, Outer Write-Through Non-transient.
0b11RWNormal memory, Outer Write-Back Non-transient.

R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.

The meaning of bits [3:0] depends on the value of bits [7:4]:

Attr<n>[3:0]Meaning when Attr<n>[7:4] is 0b0000Meaning when Attr<n>[7:4] is not 0b0000
0b0000Device-nGnRnE memoryUNPREDICTABLE
0b00RW, RW not 0b00UNPREDICTABLENormal memory, Inner Write-Through Transient
0b0100Device-nGnRE memoryNormal memory, Inner Non-cacheable
0b01RW, RW not 0b00UNPREDICTABLENormal memory, Inner Write-Back Transient
0b1000Device-nGRE memoryNormal memory, Inner Write-Through Non-transient (RW=0b00)
0b10RW, RW not 0b00UNPREDICTABLENormal memory, Inner Write-Through Non-transient
0b1100Device-GRE memoryNormal memory, Inner Write-Back Non-transient (RW=0b00)
0b11RW, RW not 0b00UNPREDICTABLENormal memory, Inner Write-Back Non-transient

R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.

The R and W bits in some Attr<n> fields have the following meanings:

R or WMeaning
0b0No Allocate
0b1Allocate

When FEAT_XS is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.

The reset behavior of this field is:

Accessing MAIR1

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b10100b00100b001

if !IsFeatureImplemented(FEAT_AA32EL1) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T10 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR.TRVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then R[t] = MAIR1_NS; else R[t] = NMRR_NS; else if TTBCR.EAE == '1' then R[t] = MAIR1; else R[t] = NMRR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then R[t] = MAIR1_NS; else R[t] = NMRR_NS; else if TTBCR.EAE == '1' then R[t] = MAIR1; else R[t] = NMRR; elsif PSTATE.EL == EL3 then if TTBCR.EAE == '1' then if SCR.NS == '0' then R[t] = MAIR1_S; else R[t] = MAIR1_NS; else if SCR.NS == '0' then R[t] = NMRR_S; else R[t] = NMRR_NS;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b10100b00100b001

if !IsFeatureImplemented(FEAT_AA32EL1) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T10 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR.TVM == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then MAIR1_NS = R[t]; else NMRR_NS = R[t]; else if TTBCR.EAE == '1' then MAIR1 = R[t]; else NMRR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then if TTBCR.EAE == '1' then MAIR1_NS = R[t]; else NMRR_NS = R[t]; else if TTBCR.EAE == '1' then MAIR1 = R[t]; else NMRR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' && CP15SDISABLE == HIGH then UNDEFINED; elsif SCR.NS == '0' && CP15SDISABLE2 == HIGH then UNDEFINED; else if TTBCR.EAE == '1' then if SCR.NS == '0' then MAIR1_S = R[t]; else MAIR1_NS = R[t]; else if SCR.NS == '0' then NMRR_S = R[t]; else NMRR_NS = R[t];