Interrupt Controller Virtual Interrupt Group 0 Enable register
Controls whether virtual Group 0 interrupts are enabled or not.
AArch32 System register ICV_IGRPEN0 bits [31:0] are architecturally mapped to AArch64 System register ICV_IGRPEN0_EL1[31:0].
This register is present only when FEAT_AA32EL1 is implemented, GICv3 is implemented, and EL2 is implemented. Otherwise, direct accesses to ICV_IGRPEN0 are UNDEFINED.
ICV_IGRPEN0 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | Enable | ||||||||||||||||||||||||||||||
Reserved, RES0.
Enables virtual Group 0 interrupts.
| Enable | Meaning |
|---|---|
| 0b0 |
Virtual Group 0 interrupts are disabled. |
| 0b1 |
Virtual Group 0 interrupts are enabled. |
The reset behavior of this field is:
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b1100, CRm = 0b1100, opc2 = 0b110)
if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL IN {EL1, EL2} && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().FIQ == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL IN {EL1, EL2} && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().FIQ == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif ICC_SRE().SRE == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TALL0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TALL0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().FMO == '1' then R(t) = ICV_IGRPEN0(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().FMO == '1' then R(t) = ICV_IGRPEN0(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().FIQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().FIQ == '1' then Undefined(); else R(t) = ICC_IGRPEN0(); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().FIQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().FIQ == '1' then Undefined(); else R(t) = ICC_IGRPEN0(); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); elsif SCR().FIQ == '1' && PSTATE.M != M32_Monitor then Undefined(); else R(t) = ICC_IGRPEN0(); end; end;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b1100, CRm = 0b1100, opc2 = 0b110)
if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif HaveEL(EL3) && PSTATE.EL IN {EL1, EL2} && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().FIQ == '1' then Undefined(); elsif HaveEL(EL3) && PSTATE.EL IN {EL1, EL2} && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().FIQ == '1' then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif ICC_SRE().SRE == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TALL0 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TALL0 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().FMO == '1' then ICV_IGRPEN0() = R(t); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().FMO == '1' then ICV_IGRPEN0() = R(t); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().FIQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().FIQ == '1' then Undefined(); else ICC_IGRPEN0() = R(t); end; elsif PSTATE.EL == EL2 then if ICC_HSRE().SRE == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().FIQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().FIQ == '1' then Undefined(); else ICC_IGRPEN0() = R(t); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); elsif SCR().FIQ == '1' && PSTATE.M != M32_Monitor then Undefined(); else ICC_IGRPEN0() = R(t); end; end;
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