Interrupt Controller Monitor Interrupt Group 1 Enable register
Controls whether Group 1 interrupts are enabled or not.
This register is present only when FEAT_AA32EL3 is implemented, GICv3 is implemented, and EL3 is implemented. Otherwise, direct accesses to ICC_MGRPEN1 are UNDEFINED.
ICC_MGRPEN1 is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | EnableGrp1S | EnableGrp1NS | |||||||||||||||||||||||||||||
Reserved, RES0.
Enables Group 1 interrupts for the Secure state.
| EnableGrp1S | Meaning |
|---|---|
| 0b0 |
Secure Group 1 interrupts are disabled. |
| 0b1 |
Secure Group 1 interrupts are enabled. |
The Secure ICC_IGRPEN1.Enable bit is a read/write alias of the ICC_MGRPEN1.EnableGrp1S bit.
If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.
The reset behavior of this field is:
Enables Group 1 interrupts for the Non-secure state.
| EnableGrp1NS | Meaning |
|---|---|
| 0b0 |
Non-secure Group 1 interrupts are disabled. |
| 0b1 |
Non-secure Group 1 interrupts are enabled. |
The Non-secure ICC_IGRPEN1.Enable bit is a read/write alias of the ICC_MGRPEN1.EnableGrp1NS bit.
If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0.
The reset behavior of this field is:
If an interrupt is pending within the CPU interface when an Enable bit becomes 0, the interrupt must be released to allow the Distributor to forward the interrupt to a different PE.
This register is only accessible when executing in Monitor mode.
Accesses to this register use the following encodings in the System register encoding space:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b110, CRn = 0b1100, CRm = 0b1100, opc2 = 0b111)
if !(IsFeatureImplemented(FEAT_AA32EL3) && IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else R[t] = ICC_MGRPEN1;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b110, CRn = 0b1100, CRm = 0b1100, opc2 = 0b111)
if !(IsFeatureImplemented(FEAT_AA32EL3) && IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3)) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else ICC_MGRPEN1 = R[t];
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