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DSPSR2

Debug Saved Process State Register 2

Holds the saved process state for Debug state. On entering Debug state, PSTATE information is written to this register. On exiting Debug state, values are copied from this register to PSTATE.

Configuration

AArch32 System register DSPSR2 bits [31:0] are architecturally mapped to AArch64 System register DSPSR_EL0[63:32] when FEAT_Debugv8p9 is implemented.

This register is present only when FEAT_Debugv8p9 is implemented and FEAT_AA32 is implemented. Otherwise, direct accesses to DSPSR2 are UNDEFINED.

Attributes

DSPSR2 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0UINJRES0PPENDRES0

Bits [31:5]:

Reserved, RES0.

UINJ, bit [4] when FEAT_UINJ is implemented:

Inject Undefined Instruction exception. Set to the value of PSTATE.UINJ on entering Debug state, and copied to PSTATE.UINJ on exiting Debug state.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bits [3:2]:

Reserved, RES0.

PPEND, bit [1] when FEAT_SEBEP is implemented:

PMU Profiling exception pending bit. Set to the value of PSTATE.PPEND on entering Debug state, and conditionally copied to PSTATE.PPEND on exiting Debug state.

The reset behavior of this field is:

Otherwise:

Reserved, RES0.

Bit [0]:

Reserved, RES0.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

(coproc = 0b1111, opc1 = 0b011, CRn = 0b0100, CRm = 0b0101, opc2 = 0b010)

if !(IsFeatureImplemented(FEAT_Debugv8p9) && IsFeatureImplemented(FEAT_AA32)) then UNDEFINED; elsif !Halted() then UNDEFINED; else R[t] = DSPSR2;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

(coproc = 0b1111, opc1 = 0b011, CRn = 0b0100, CRm = 0b0101, opc2 = 0b010)

if !(IsFeatureImplemented(FEAT_Debugv8p9) && IsFeatureImplemented(FEAT_AA32)) then UNDEFINED; elsif !Halted() then UNDEFINED; else DSPSR2 = R[t];

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