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DBGVCR

Debug Vector Catch Register

Controls Vector Catch debug events.

Configuration

AArch32 System register DBGVCR bits [31:0] are architecturally mapped to AArch64 System register DBGVCR32_EL2[31:0].

This register is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to DBGVCR are UNDEFINED.

This register is required in all implementations.

Attributes

DBGVCR is a 32-bit register.

Field descriptions

When EL3 is implemented and EL3 is using AArch32:

313029282726252423222120191817161514131211109876543210
NSFNSIRES0NSDNSPNSSNSURES0MFMIRES0MDMPMSRES0SFSIRES0SDSPSSSURES0

NSF, bit [31]:

FIQ vector catch enable in Non-secure state.

The exception vector offset is 0x1C.

The reset behavior of this field is:

NSI, bit [30]:

IRQ vector catch enable in Non-secure state.

The exception vector offset is 0x18.

The reset behavior of this field is:

Bit [29]:

Reserved, RES0.

NSD, bit [28]:

Data Abort exception vector catch enable in Non-secure state.

The exception vector offset is 0x10.

The reset behavior of this field is:

NSP, bit [27]:

Prefetch Abort vector catch enable in Non-secure state.

The exception vector offset is 0x0C.

The reset behavior of this field is:

NSS, bit [26]:

Supervisor Call (SVC) vector catch enable in Non-secure state.

The exception vector offset is 0x08.

The reset behavior of this field is:

NSU, bit [25]:

Undefined Instruction vector catch enable in Non-secure state.

The exception vector offset is 0x04.

The reset behavior of this field is:

Bits [24:16]:

Reserved, RES0.

MF, bit [15]:

FIQ vector catch enable in Monitor mode.

The exception vector offset is 0x1C.

The reset behavior of this field is:

MI, bit [14]:

IRQ vector catch enable in Monitor mode.

The exception vector offset is 0x18.

The reset behavior of this field is:

Bit [13]:

Reserved, RES0.

MD, bit [12]:

Data Abort exception vector catch enable in Monitor mode.

The exception vector offset is 0x10.

The reset behavior of this field is:

MP, bit [11]:

Prefetch Abort vector catch enable in Monitor mode.

The exception vector offset is 0x0C.

The reset behavior of this field is:

MS, bit [10]:

Secure Monitor Call (SMC) vector catch enable in Monitor mode.

The exception vector offset is 0x08.

The reset behavior of this field is:

Bits [9:8]:

Reserved, RES0.

SF, bit [7]:

FIQ vector catch enable in Secure state.

The exception vector offset is 0x1C.

The reset behavior of this field is:

SI, bit [6]:

IRQ vector catch enable in Secure state.

The exception vector offset is 0x18.

The reset behavior of this field is:

Bit [5]:

Reserved, RES0.

SD, bit [4]:

Data Abort exception vector catch enable in Secure state.

The exception vector offset is 0x10.

The reset behavior of this field is:

SP, bit [3]:

Prefetch Abort vector catch enable in Secure state.

The exception vector offset is 0x0C.

The reset behavior of this field is:

SS, bit [2]:

Supervisor Call (SVC) vector catch enable in Secure state.

The exception vector offset is 0x08.

The reset behavior of this field is:

SU, bit [1]:

Undefined Instruction vector catch enable in Secure state.

The exception vector offset is 0x04.

The reset behavior of this field is:

Bit [0]:

Reserved, RES0.

When EL3 is implemented and EL3 is using AArch64:

313029282726252423222120191817161514131211109876543210
NSFNSIRES0NSDNSPNSSNSURES0SFSIRES0SDSPSSSURES0

NSF, bit [31]:

FIQ vector catch enable in Non-secure state.

The exception vector offset is 0x1C.

The reset behavior of this field is:

NSI, bit [30]:

IRQ vector catch enable in Non-secure state.

The exception vector offset is 0x18.

The reset behavior of this field is:

Bit [29]:

Reserved, RES0.

NSD, bit [28]:

Data Abort exception vector catch enable in Non-secure state.

The exception vector offset is 0x10.

The reset behavior of this field is:

NSP, bit [27]:

Prefetch Abort vector catch enable in Non-secure state.

The exception vector offset is 0x0C.

The reset behavior of this field is:

NSS, bit [26]:

Supervisor Call (SVC) vector catch enable in Non-secure state.

The exception vector offset is 0x08.

The reset behavior of this field is:

NSU, bit [25]:

Undefined Instruction vector catch enable in Non-secure state.

The exception vector offset is 0x04.

The reset behavior of this field is:

Bits [24:8]:

Reserved, RES0.

SF, bit [7]:

FIQ vector catch enable in Secure state.

The exception vector offset is 0x1C.

The reset behavior of this field is:

SI, bit [6]:

IRQ vector catch enable in Secure state.

The exception vector offset is 0x18.

The reset behavior of this field is:

Bit [5]:

Reserved, RES0.

SD, bit [4]:

Data Abort exception vector catch enable in Secure state.

The exception vector offset is 0x10.

The reset behavior of this field is:

SP, bit [3]:

Prefetch Abort vector catch enable in Secure state.

The exception vector offset is 0x0C.

The reset behavior of this field is:

SS, bit [2]:

Supervisor Call (SVC) vector catch enable in Secure state.

The exception vector offset is 0x08.

The reset behavior of this field is:

SU, bit [1]:

Undefined Instruction vector catch enable in Secure state.

The exception vector offset is 0x04.

The reset behavior of this field is:

Bit [0]:

Reserved, RES0.

When EL3 is not implemented:

313029282726252423222120191817161514131211109876543210
RES0FIRES0DPSURES0

Bits [31:8]:

Reserved, RES0.

F, bit [7]:

FIQ vector catch enable.

The exception vector offset is 0x1C.

The reset behavior of this field is:

I, bit [6]:

IRQ vector catch enable.

The exception vector offset is 0x18.

The reset behavior of this field is:

Bit [5]:

Reserved, RES0.

D, bit [4]:

Data Abort exception vector catch enable.

The exception vector offset is 0x10.

The reset behavior of this field is:

P, bit [3]:

Prefetch Abort vector catch enable.

The exception vector offset 0x0C.

The reset behavior of this field is:

S, bit [2]:

Supervisor Call (SVC) vector catch enable.

The exception vector offset is 0x08.

The reset behavior of this field is:

U, bit [1]:

Undefined Instruction vector catch enable.

The exception vector offset is 0x04.

The reset behavior of this field is:

Bit [0]:

Reserved, RES0.

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

(coproc = 0b1110, opc1 = 0b000, CRn = 0b0000, CRm = 0b0111, opc2 = 0b000)

if !IsFeatureImplemented(FEAT_AA32EL1) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGVCR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else R[t] = DBGVCR; elsif PSTATE.EL == EL3 then R[t] = DBGVCR;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

(coproc = 0b1110, opc1 = 0b000, CRn = 0b0000, CRm = 0b0111, opc2 = 0b000)

if !IsFeatureImplemented(FEAT_AA32EL1) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then AArch64.AArch32SystemAccessTrap(EL2, 0x05); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HDCR.<TDE,TDA> != '00' then AArch32.TakeHypTrapException(0x05); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGVCR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x05); else DBGVCR = R[t]; elsif PSTATE.EL == EL3 then DBGVCR = R[t];

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