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DACR

Domain Access Control Register

Defines the access permission for each of the sixteen memory domains.

Configuration

This register is banked between DACR and DACR_S and DACR_NS.

AArch32 System register DACR bits [31:0] are architecturally mapped to AArch64 System register DACR32_EL2[31:0].

This register is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to DACR are UNDEFINED.

This register has no function when TTBCR.EAE is set to 1, to select the Long-descriptor translation table format.

Attributes

DACR is a 32-bit register.

This register has the following instances:

Field descriptions

313029282726252423222120191817161514131211109876543210
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

D<n>, bits [2n+1:2n], for n = 15 to 0:

Domain n access permission, where n = 0 to 15. Permitted values are:

D<n>Meaning
0b00

No access. Any access to the domain generates a Domain fault.

0b01

Client. Accesses are checked against the permission bits in the translation tables.

0b11

Manager. Accesses are not checked against the permission bits in the translation tables.

The value 0b10 is reserved.

The reset behavior of this field is:

Access Instructions

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

(coproc = 0b1111, opc1 = 0b000, CRn = 0b0011, CRm = 0b0000, opc2 = 0b000)

if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T3 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TRVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TRVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = DACR_NS(); else R(t) = DACR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then R(t) = DACR_NS(); else R(t) = DACR(); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' then R(t) = DACR_S(); else R(t) = DACR_NS(); end; end;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

(coproc = 0b1111, opc1 = 0b000, CRn = 0b0011, CRm = 0b0000, opc2 = 0b000)

if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T3 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T3 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TVM == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TVM == '1' then AArch32_TakeHypTrapException(0x03); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then DACR_NS() = R(t); else DACR() = R(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) then DACR_NS() = R(t); else DACR() = R(t); end; elsif PSTATE.EL == EL3 then if SCR().NS == '0' && CP15SDISABLE == HIGH then Undefined(); elsif SCR().NS == '0' && CP15SDISABLE2 == HIGH then Undefined(); else if SCR().NS == '0' then DACR_S() = R(t); else DACR_NS() = R(t); end; end; end;

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