Data Synchronization Barrier System instruction
Performs a Data Synchronization Barrier.
Arm deprecates any use of this System instruction, and strongly recommends that software use the DSB instruction instead.
This instruction is present only when FEAT_AA32 is implemented. Otherwise, direct accesses to CP15DSB are UNDEFINED.
CP15DSB is a 32-bit System instruction.
This instruction has no applicable fields.
The value in the register specified by <Rt> is ignored.
Accesses to this instruction use the following encodings in the System instruction encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b0111, CRm = 0b1010, opc2 = 0b100)
if !IsFeatureImplemented(FEAT_AA32) then UNDEFINED; elsif PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_AA64EL1) && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && SCTLR_EL1.CP15BEN == '0' then UNDEFINED; elsif ELIsInHost(EL0) && SCTLR_EL2.CP15BEN == '0' then UNDEFINED; elsif IsFeatureImplemented(FEAT_AA32EL1) && ELUsingAArch32(EL1) && SCTLR.CP15BEN == '0' then UNDEFINED; elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2)) && !ELIsInHost(EL0) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && (IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2)) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); else CP15DSB(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); elsif SCTLR.CP15BEN == '0' then UNDEFINED; else CP15DSB(); elsif PSTATE.EL == EL2 then if HSCTLR.CP15BEN == '0' then UNDEFINED; else CP15DSB(); elsif PSTATE.EL == EL3 then if SCTLR.CP15BEN == '0' then UNDEFINED; else CP15DSB();
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