Address Translate Stage 1 Current state PL1 Read
Performs stage 1 address translation as defined for PL1 and the current Security state, with permissions as if reading from the given virtual address.
This instruction is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to ATS1CPR are UNDEFINED.
ATS1CPR is a 32-bit System instruction.
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Input address for translation. The resulting address can be read from the PAR.
This System instruction takes a VA as input. If EL2 is implemented and enabled in the current Security state, the resulting address is the IPA that is the output address of the stage 1 translation. Otherwise, the resulting address is a PA.
Accesses to this instruction use the following encodings in the System instruction encoding space:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
(coproc = 0b1111, opc1 = 0b000, CRn = 0b0111, CRm = 0b1000, opc2 = 0b000)
if !IsFeatureImplemented(FEAT_AA32EL1) then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR.T7 == '1' then AArch32.TakeHypTrapException(0x03); else AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_Read); elsif PSTATE.EL == EL2 then AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_Read); elsif PSTATE.EL == EL3 then if SCR.NS == '0' then AArch32.AT(R[t], TranslationStage_1, EL3, ATAccess_Read); else AArch32.AT(R[t], TranslationStage_1, EL1, ATAccess_Read);
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