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UXTB, UXTH, UXTW

Unsigned byte / halfword / word extend (predicated)

This instruction zero-extends the least-significant sub-element of each active element of the source vector, and places the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.

It has encodings from 6 classes: Byte, merging , Byte, zeroing , Halfword, merging , Halfword, zeroing , Word, merging and Word, zeroing

Byte, merging class

(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000100size010001101PgZnZd
MU

Encoding

UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); if size == '00' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer s_esize = 8; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = TRUE; constant boolean merging = TRUE;

Byte, zeroing class

(FEAT_SVE2p2 || FEAT_SME2p2)

313029282726252423222120191817161514131211109876543210
00000100size000001101PgZnZd
MU

Encoding

UXTB <Zd>.<T>, <Pg>/Z, <Zn>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); if size == '00' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer s_esize = 8; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = TRUE; constant boolean merging = FALSE;

Halfword, merging class

(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000100size010011101PgZnZd
MU

Encoding

UXTH <Zd>.<T>, <Pg>/M, <Zn>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); if size IN {'0x'} then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer s_esize = 16; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = TRUE; constant boolean merging = TRUE;

Halfword, zeroing class

(FEAT_SVE2p2 || FEAT_SME2p2)

313029282726252423222120191817161514131211109876543210
00000100size000011101PgZnZd
MU

Encoding

UXTH <Zd>.<T>, <Pg>/Z, <Zn>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); if size IN {'0x'} then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer s_esize = 16; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = TRUE; constant boolean merging = FALSE;

Word, merging class

(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00000100size010101101PgZnZd
MU

Encoding

UXTW <Zd>.D, <Pg>/M, <Zn>.D

Decode

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); if size != '11' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer s_esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = TRUE; constant boolean merging = TRUE;

Word, zeroing class

(FEAT_SVE2p2 || FEAT_SME2p2)

313029282726252423222120191817161514131211109876543210
00000100size000101101PgZnZd
MU

Encoding

UXTW <Zd>.D, <Pg>/Z, <Zn>.D

Decode

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then EndOfDecode(Decode_UNDEF); if size != '11' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer s_esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = TRUE; constant boolean merging = FALSE;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

For the "Byte, merging" and "Byte, zeroing" variants: is the size specifier, encoded in size:

size <T>
00 RESERVED
01 H
10 S
11 D

For the "Halfword, merging" and "Halfword, zeroing" variants: is the size specifier, encoded in size<0>:

size<0> <T>
0 S
1 D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(VL) result = if merging then Z[d, VL] else Zeros(VL); for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(esize) element = Elem[operand, e, esize]; Elem[result, e, esize] = Extend(element<s_esize-1:0>, esize, unsigned); Z[d, VL] = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

The merging variant of this instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and the merging variant of this instruction is CONSTRAINED UNPREDICTABLE:

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