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UQDECP (scalar)

Unsigned saturating decrement scalar by count of true predicate elements

This instruction determines the number of true elements in the source predicate and then uses the result to decrement the scalar destination. The result is saturated to the general-purpose register's unsigned integer range.

It has encodings from 2 classes: 32-bit and 64-bit

32-bit class

(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00100101size1010111000100PmRdn
DUsfop

Encoding

UQDECP <Wdn>, <Pm>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let m : integer = UInt(Pm); let dn : integer = UInt(Rdn); let unsigned : boolean = TRUE; let ssize : integer{} = 32;

64-bit class

(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
00100101size1010111000110PmRdn
DUsfop

Encoding

UQDECP <Xdn>, <Pm>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let m : integer = UInt(Pm); let dn : integer = UInt(Rdn); let unsigned : boolean = TRUE; let ssize : integer{} = 64;

Assembler Symbols

<Wdn>

Is the 32-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

<Pm>

Is the name of the source scalable predicate register, encoded in the "Pm" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Xdn>

Is the 64-bit name of the source and destination general-purpose register, encoded in the "Rdn" field.

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; let operand1 : bits(ssize) = X{}(dn); let operand2 : bits(PL) = P{}(m); var result : bits(ssize); var count : integer = 0; for e = 0 to elements-1 do if ActivePredicateElement{PL}(operand2, e, esize) then count = count + 1; end; end; if unsigned then (result, -) = UnsignedSatQ{ssize}(UInt(operand1) - count); X{64}(dn) = ZeroExtend{64}(result); else (result, -) = SignedSatQ{ssize}(SInt(operand1) - count); X{64}(dn) = SignExtend{64}(result); end;

Operational information

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction that is dependent on the general-purpose register written by this instruction might be significantly delayed.


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