UCVTFLT

Unsigned integer convert to floating-point (top, unpredicated)

This instruction converts each odd-numbered unsigned integer element of the source vector to floating-point, and places the results in the overlapping double-width elements of the destination vector.

This instruction is unpredicated.

SVE2 class

(FEAT_SVE2p3 || FEAT_SME2p3)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	size		0	0	1	1	0	0	0	0	1	1	1	1	Zn					Zd
																					U

Encoding

UCVTFLT <Zd>.<T>, <Zn>.<Tb>

Decode

if !IsFeatureImplemented(FEAT_SVE2p3) && !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); if size == '00' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant boolean unsigned = TRUE; constant FPRounding rounding = FPRoundingMode(FPCR);

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	RESERVED
01	H
10	S
11	D

<Zn>	Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size:

size	<Tb>
00	RESERVED
01	B
10	H
11	S

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(VL) operand = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(esize DIV 2) element = Elem[operand, 2*e + 1, esize DIV 2]; Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding, esize); Z[d, VL] = result;