UABA

Unsigned absolute difference and accumulate

This instruction computes the absolute difference between unsigned integer values in elements of the second source vector and corresponding elements of the first source vector, and adds the difference to the corresponding elements of the destination vector. This instruction is unpredicated.

SVE2 class

(FEAT_SVE2 || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	1	size		0	Zm					1	1	1	1	1	1	Zn					Zda
																					U

Encoding

UABA <Zda>.<T>, <Zn>.<T>, <Zm>.<T>

Decode

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda); constant boolean unsigned = TRUE;

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	B
01	H
10	S
11	D

<Zn>	Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>	Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; bits(VL) result = Z[da, VL]; for e = 0 to elements-1 constant bits(esize) op1elt = Elem[operand1, e, esize]; constant bits(esize) op2elt = Elem[operand2, e, esize]; constant integer element1 = if unsigned then UInt(op1elt) else SInt(op1elt); constant integer element2 = if unsigned then UInt(op2elt) else SInt(op2elt); constant bits(esize) absdiff = Abs(element1 - element2)<esize-1:0>; Elem[result, e, esize] = Elem[result, e, esize] + absdiff; Z[da, VL] = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:

The MOVPRFX must be unpredicated.
The MOVPRFX must specify the same destination register as this instruction.
The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

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