System instruction with result
For more information, see Op0 equals 0b01, cache maintenance, TLB maintenance, and address translation instructions for the encodings of System instructions.
This instruction is used by the aliases GCSPOPM, and GCSSS2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | op1 | CRn | CRm | op2 | Rt | ||||||||||||||
| L | |||||||||||||||||||||||||||||||
constant integer t = UInt(Rt); constant bits(1) sys_L = L; constant bits(2) sys_op0 = '01'; constant bits(3) sys_op1 = op1; constant bits(3) sys_op2 = op2; constant bits(4) sys_crn = CRn; constant bits(4) sys_crm = CRm;
| <Xt> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Rt" field. |
| <op1> |
Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field. |
| <Cn> |
Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field. |
| <Cm> |
Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field. |
| <op2> |
Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field. |
| Alias | Is preferred when |
|---|---|
| GCSPOPM | op1 == '011' && CRn == '0111' && CRm == '0111' && op2 == '001' |
| GCSSS2 | op1 == '011' && CRn == '0111' && CRm == '0111' && op2 == '011' |
AArch64.CheckSystemAccess(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t, sys_L); AArch64.SysInstrWithResult(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t);