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STTSET, STTSETL

Atomic bit set unprivileged, without return

This instruction atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory.

For information about addressing modes, see Load/Store addressing modes.

This is an alias of LDTSET, LDTSETA, LDTSETAL, LDTSETL. This means:

Integer class

(FEAT_LSUI)

313029282726252423222120191817161514131211109876543210
0sz0110010R1Rs001101Rn11111
Ao3opcRt

32-bit no memory ordering encoding

(sz == 0 && R == 0)

STTSET <Ws>, [<Xn|SP>]

is equivalent to

LDTSET <Ws>, WZR, [<Xn|SP>]

and is always the preferred disassembly.

32-bit release encoding

(sz == 0 && R == 1)

STTSETL <Ws>, [<Xn|SP>]

is equivalent to

LDTSETL <Ws>, WZR, [<Xn|SP>]

and is always the preferred disassembly.

64-bit no memory ordering encoding

(sz == 1 && R == 0)

STTSET <Xs>, [<Xn|SP>]

is equivalent to

LDTSET <Xs>, XZR, [<Xn|SP>]

and is always the preferred disassembly.

64-bit release encoding

(sz == 1 && R == 1)

STTSETL <Xs>, [<Xn|SP>]

is equivalent to

LDTSETL <Xs>, XZR, [<Xn|SP>]

and is always the preferred disassembly.

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xs>

Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

Operation

The description of LDTSET, LDTSETA, LDTSETAL, LDTSETL gives the operational pseudocode for this instruction.

Operational Information

The description of LDTSET, LDTSETA, LDTSETAL, LDTSETL gives the operational information for this instruction.

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