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STP (SIMD&FP)

Store pair of SIMD&FP registers

This instruction stores a pair of SIMD&FP registers to memory. The address used for the store is calculated from a base register value and an immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 3 classes: Post-index , Pre-index and Signed offset

Post-index class

(FEAT_FP)

313029282726252423222120191817161514131211109876543210
opc10110010imm7Rt2RnRt
VRL

32-bit encoding

(opc == 00)

STP <St1>, <St2>, [<Xn|SP>], #<imm>

64-bit encoding

(opc == 01)

STP <Dt1>, <Dt2>, [<Xn|SP>], #<imm>

128-bit encoding

(opc == 10)

STP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>

Decode (all encodings)

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); constant boolean wback = TRUE; constant boolean postindex = TRUE;

Pre-index class

(FEAT_FP)

313029282726252423222120191817161514131211109876543210
opc10110110imm7Rt2RnRt
VRL

32-bit encoding

(opc == 00)

STP <St1>, <St2>, [<Xn|SP>, #<imm>]!

64-bit encoding

(opc == 01)

STP <Dt1>, <Dt2>, [<Xn|SP>, #<imm>]!

128-bit encoding

(opc == 10)

STP <Qt1>, <Qt2>, [<Xn|SP>, #<imm>]!

Decode (all encodings)

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); constant boolean wback = TRUE; constant boolean postindex = FALSE;

Signed offset class

(FEAT_FP)

313029282726252423222120191817161514131211109876543210
opc10110100imm7Rt2RnRt
VRL

32-bit encoding

(opc == 00)

STP <St1>, <St2>, [<Xn|SP>{, #<imm>}]

64-bit encoding

(opc == 01)

STP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]

128-bit encoding

(opc == 10)

STP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]

Decode (all encodings)

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); constant boolean wback = FALSE; constant boolean postindex = FALSE;

Assembler Symbols

<St1>

Is the 32-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.

<St2>

Is the 32-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

For the "Post-index 32-bit" and "Pre-index 32-bit" variants: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.

For the "Post-index 64-bit" and "Pre-index 64-bit" variants: is the signed immediate byte offset, a multiple of 8 in the range -512 to 504, encoded in the "imm7" field as <imm>/8.

For the "Post-index 128-bit" and "Pre-index 128-bit" variants: is the signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, encoded in the "imm7" field as <imm>/16.

For the "Signed offset 32-bit" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.

For the "Signed offset 64-bit" variant: is the optional signed immediate byte offset, a multiple of 8 in the range -512 to 504, defaulting to 0 and encoded in the "imm7" field as <imm>/8.

For the "Signed offset 128-bit" variant: is the optional signed immediate byte offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "imm7" field as <imm>/16.

<Dt1>

Is the 64-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.

<Dt2>

Is the 64-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

<Qt1>

Is the 128-bit name of the first SIMD&FP register to be transferred, encoded in the "Rt" field.

<Qt2>

Is the 128-bit name of the second SIMD&FP register to be transferred, encoded in the "Rt2" field.

Shared Decode

constant integer t = UInt(Rt); constant integer t2 = UInt(Rt2); constant integer n = UInt(Rn); constant boolean nontemporal = FALSE; constant integer scale = 2 + (UInt(opc)); constant integer datasize = 8 << scale; constant bits(64) offset = LSL(SignExtend(imm7, 64), scale); constant boolean tagchecked = wback || n != 31;

Operation

AArch64.CheckFPEnabled(); bits(64) address; constant integer dbytes = datasize DIV 8; constant boolean privileged = PSTATE.EL != EL0; constant boolean ispair = TRUE; constant AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked, privileged, ispair); if n == 31 then CheckSPAlignment(); address = SP[64]; else address = X[n, 64]; if !postindex then address = AddressAdd(address, offset, accdesc); bits(2*datasize) data; if BigEndian(accdesc.acctype) then data = V[t, datasize] : V[t2, datasize]; else data = V[t2, datasize] : V[t, datasize]; Mem[address, 2*dbytes, accdesc] = data; if wback then if postindex then address = AddressAdd(address, offset, accdesc); if n == 31 then SP[64] = address; else X[n, 64] = address;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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