STLP

Store-release pair of registers

This instruction calculates an address from a base register value, and stores two 64-bit doublewords to the calculated address, from two registers. Explicit Memory effects produced by this instruction have Release semantics. For information about memory ordering semantics, see Load-Acquire, Load-AcquirePC, and Store-Release.

For information about addressing modes, see Load/Store addressing modes.

No offset class

(FEAT_LSCP)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	1	0	0	1	0	0	0	Rt2					0	1	0	1	1	0	Rn					Rt
size									L							opc2

Encoding

STLP <Xt1>, <Xt2>, [<Xn|SP>{, #0}]

Decode

if !IsFeatureImplemented(FEAT_LSCP) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Rt); constant integer t2 = UInt(Rt2); constant integer n = UInt(Rn); constant boolean acquire = FALSE; constant boolean tagchecked = n != 31; constant boolean ispair = TRUE;

Assembler Symbols

<Xt1>

Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Xt2>

Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

bits(64) address; bits(64) data1; bits(64) data2; constant boolean privileged = PSTATE.EL != EL0; constant AccessDescriptor accdesc = CreateAccDescAcqRel(MemOp_STORE, tagchecked, ispair, acquire, t, t2); if n == 31 then CheckSPAlignment(); address = SP[64]; else address = X[n, 64]; data1 = X[t, 64]; data2 = X[t2, 64]; constant bits(128) full_data = (if BigEndian(accdesc.acctype) then data1:data2 else data2:data1); Mem[address, 16, accdesc] = full_data;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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