STL64B

Single-copy atomic 64-byte store-release without status result

This instruction stores eight 64-bit doublewords from consecutive registers to a memory location. The store starts at register Xt, with the data being formed as Data[511:0] = X(t+7)::X(t+6)::X(t+5)::X(t+4)::X(t+3)::X(t+2)::X(t+1)::Xt. The data is stored atomically and is required to be 64-byte aligned.

It is IMPLEMENTATION DEFINED which memory locations support this instruction. A memory location that supports STL64B also supports LD64B, LDA64B, and ST64B.

STL64B stores to memory with release semantics.

For more information, including about the memory types accessible and how the accesses are performed, see Single-copy atomic 64-byte load/store.

Integer class

(FEAT_LS64 && FEAT_LSC64B)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	0	0	0	1	1	1	1	1	1	1	1	0	0	1	0	0	Rn					Rt
size					VR			A	R		Rs					o3	opc

Encoding

STL64B <Xt>, [<Xn|SP> {, #0}]

Decode

if !IsFeatureImplemented(FEAT_LSC64B) then EndOfDecode(Decode_UNDEF); end; if !IsFeatureImplemented(FEAT_LS64) then EndOfDecode(Decode_UNDEF); end; if Rt[4:3] == '11' || Rt[0] == '1' then EndOfDecode(Decode_UNDEF); end; let withstatus : boolean = FALSE; let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let tagchecked : boolean = n != 31; let acqrel : boolean = TRUE;

STL64B has the same CONSTRAINED UNPREDICTABLE behavior as ST64B. For information about this CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly ST64B.

Assembler Symbols

<Xt>	Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

CheckLDST64BEnabled(acqrel); var data : bits(512); var address : bits(64); var value : bits(64); let accdesc : AccessDescriptor = CreateAccDescLS64(MemOp_STORE, withstatus, acqrel, tagchecked); for i = 0 to 7 do value = X{64}(t+i); if BigEndian(accdesc.acctype) then value = BigEndianReverse{64}(value); end; data[63+64*i : 64*i] = value; end; if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; MemStore64B(address, data, accdesc);