STCPH

Store concurrent priority hint

This instruction signals to the memory system that if the next instruction in program order generates an Explicit Memory Write Effect, then there is a performance benefit if that Explicit Memory Write Effect is sequenced before Memory Effects from other threads of execution in the coherence order to the same location. For atomic instructions, there is a performance benefit if the corresponding Explicit Memory Read Effect is sequenced before Memory Effects from other threads of execution in the coherence order to the same location. This includes cases in which any instruction that conditionally performs a write generates an Explicit Memory Read Effect before it is known whether the write is performed.

System class

(FEAT_CMH)

Decode

if !IsFeatureImplemented(FEAT_CMH) then EndOfDecode(Decode_NOP);

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