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ST1W (scalar plus vector)

Scatter store words from a vector (vector index)

This instruction performs a scatter store of words from the Active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign-extended or zero-extended from 32 to 64 bits and then optionally multiplied by 4. Inactive elements are not written to memory.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 6 classes: 32-bit scaled offset , 32-bit unpacked scaled offset , 32-bit unpacked unscaled offset , 32-bit unscaled offset , 64-bit scaled offset and 64-bit unscaled offset

32-bit scaled offset class

(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11100101011Zm1xs0PgRnZt
msz

Encoding

ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]

Decode

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 32; constant integer offs_size = 32; constant boolean offs_unsigned = xs == '0'; constant integer scale = 2;

32-bit unpacked scaled offset class

(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11100101001Zm1xs0PgRnZt
msz

Encoding

ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]

Decode

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 32; constant integer offs_size = 32; constant boolean offs_unsigned = xs == '0'; constant integer scale = 2;

32-bit unpacked unscaled offset class

(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11100101000Zm1xs0PgRnZt
msz

Encoding

ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]

Decode

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 32; constant integer offs_size = 32; constant boolean offs_unsigned = xs == '0'; constant integer scale = 0;

32-bit unscaled offset class

(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11100101010Zm1xs0PgRnZt
msz

Encoding

ST1W { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]

Decode

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 32; constant integer offs_size = 32; constant boolean offs_unsigned = xs == '0'; constant integer scale = 0;

64-bit scaled offset class

(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11100101001Zm101PgRnZt
msz

Encoding

ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]

Decode

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 32; constant integer offs_size = 64; constant boolean offs_unsigned = TRUE; constant integer scale = 2;

64-bit unscaled offset class

(FEAT_SVE)

313029282726252423222120191817161514131211109876543210
11100101000Zm101PgRnZt
msz

Encoding

ST1W { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]

Decode

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 32; constant integer offs_size = 64; constant boolean offs_unsigned = TRUE; constant integer scale = 0;

Assembler Symbols

<Zt>

Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Zm>

Is the name of the offset scalable vector register, encoded in the "Zm" field.

<mod>

Is the index extend and shift specifier, encoded in xs:

xs <mod>
0 UXTW
1 SXTW

Operation

CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(VL) offset; bits(VL) src; constant integer mbytes = msize DIV 8; constant boolean contiguous = FALSE; constant boolean nontemporal = FALSE; constant boolean predicated = TRUE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, predicated, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[64] else X[n, 64]; offset = Z[m, VL]; src = Z[t, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(offs_size) offselt = Elem[offset, e, esize]<offs_size-1:0>; constant integer off = if offs_unsigned then UInt(offselt) else SInt(offselt); constant bits(64) addr = AddressAdd(base, off << scale, accdesc); Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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