Scatter store quadwords
Scatter store of quadwords from the active elements of a vector register to the memory addresses generated by a vector base plus a 64-bit unscaled scalar register offset. Inactive elements are not written to memory.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | Rm | 0 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer m = UInt(Rm); constant integer g = UInt(Pg);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <Xm> |
Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. |
constant integer VL = CurrentVL; constant integer PL = VL DIV 8; CheckNonStreamingSVEEnabled(); constant integer elements = VL DIV 128; constant bits(PL) mask = P[g, PL]; bits(VL) base; bits(64) offset; bits(VL) src; constant boolean contiguous = FALSE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if AnyActiveElement(mask, 128) then base = Z[n, VL]; offset = X[m, 64]; src = Z[t, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, 128) then constant bits(64) baddr = Elem[base, 2*e, 64]; constant bits(64) addr = AddressAdd(baddr, offset, accdesc); Mem[addr, 16, accdesc] = Elem[src, e, 128];