Contiguous store doublewords from vector (scalar index)
This instruction performs a contiguous store of doublewords from elements of a vector register to the memory address generated by a 64-bit scalar base and scalar index that is multiplied by 8 and added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements are not written to memory.
The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
It has encodings from 2 classes: 64-bit element and 128-bit element
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | != 11111 | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| opc | o2 | Rm | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); if Rm == '11111' then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 64;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | != 11111 | 0 | 1 | 0 | Pg | Rn | Zt | ||||||||||||||
| opc | o2 | Rm | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); if Rm == '11111' then EndOfDecode(Decode_UNDEF); constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt(Pg); constant integer esize = 128; constant integer msize = 64;
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. |
if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(64) offset; bits(64) addr; bits(VL) src; constant integer mbytes = msize DIV 8; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean predicated = TRUE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, predicated, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); src = Z[t, VL]; base = if n == 31 then SP[64] else X[n, 64]; offset = X[m, 64]; addr = AddressAdd(base, UInt(offset) * mbytes, accdesc); for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>; addr = AddressIncrement(addr, mbytes, accdesc);
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
Version 2025.09 — Copyright © 2010-2025 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.