Signed saturating rounding shift right unsigned narrow by immediate and interleave
This instruction shifts right by an immediate value the signed integer value in each element of the two source vectors, and places the two-way interleaved rounded results in the half-width destination elements. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per destination element.
This instruction is unpredicated.
It has encodings from 2 classes: 8-bit and 16-bit
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | imm3 | 0 | 0 | 0 | 0 | 1 | 0 | Zn | 0 | Zd | |||||||||
| op0 | op1 | U | R | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2p3) && !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); constant integer esize = 8; constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd); constant integer shift = esize - UInt(imm3);
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | imm4 | 0 | 0 | 0 | 0 | 1 | 0 | Zn | 0 | Zd | ||||||||||
| op0 | op1 | U | R | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); constant integer esize = 16; constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd); constant integer shift = esize - UInt(imm4);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. |
| <Zn2> |
Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (2 * esize); bits(VL) result; for e = 0 to elements-1 for i = 0 to 1 constant bits(VL) operand = Z[n+i, VL]; constant bits(2 * esize) element = Elem[operand, e, 2 * esize]; constant integer res = (SInt(element) + (1 << (shift-1))) >> shift; Elem[result, 2*e + i, esize] = UnsignedSat(res, esize); Z[d, VL] = result;
Version 2025.09 — Copyright © 2010-2025 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.