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SQCVTUN

Multi-vector signed saturating extract narrow to interleaved unsigned integer

This instruction saturates the signed integer value in each element of the four source vectors to unsigned integer value that is quarter the original source element width, and places the four-way interleaved results in the quarter-width destination elements.

This instruction is unpredicated.

SME2 class

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001sz1110011111000Zn10Zd
opNU

Encoding

SQCVTUN <Zd>.<T>, { <Zn1>.<Tb>-<Zn4>.<Tb> }

Decode

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(sz); constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in sz:

sz <T>
0 B
1 H
<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.

<Tb>

Is the size specifier, encoded in sz:

sz <Tb>
0 S
1 D
<Zn4>

Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.

Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (4 * esize); bits(VL) result; for e = 0 to elements-1 for i = 0 to 3 constant bits(VL) operand = Z[n+i, VL]; constant integer element = SInt(Elem[operand, e, 4 * esize]); Elem[result, 4*e + i, esize] = UnsignedSat(element, esize); Z[d, VL] = result;

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