SQCVTUN

Signed 32-bit integer saturating extract narrow to interleaved unsigned 16-bit integer

This instruction saturates the signed integer value in each element of the pair of source vectors to unsigned integer value that is half the original source element width, and places the two-way interleaved results in the half-width destination elements.

This instruction is unpredicated.

SVE2 class

(FEAT_SME2 || FEAT_SVE2p1)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	0	0	0	1	0	1	0	0	1	1	0	0	0	1	0	1	0	1	0	0	Zn				0	Zd
									tszh		tszl								opc

Encoding

SQCVTUN <Zd>.H, { <Zn1>.S-<Zn2>.S }

Decode

if !IsFeatureImplemented(FEAT_SME2) && !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF); constant integer esize = 16; constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd);

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.

<Zn2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (2 * esize); bits(VL) result; for e = 0 to elements-1 for i = 0 to 1 constant bits(VL) operand = Z[n+i, VL]; constant integer element = SInt(Elem[operand, e, 2 * esize]); Elem[result, 2*e + i, esize] = UnsignedSat(element, esize); Z[d, VL] = result;