Signed saturating add (unpredicated)
This instruction performs a signed saturating addition of all elements of the second source vector to the corresponding elements of the first source vector and places the results in the corresponding elements of the destination vector. Each result element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1))-1. This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | 1 | Zm | 0 | 0 | 0 | 1 | 0 | 0 | Zn | Zd | |||||||||||||
| U | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant boolean unsigned = FALSE;
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the first source scalable vector register, encoded in the "Zn" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(esize) op1elt = Elem[operand1, e, esize]; constant bits(esize) op2elt = Elem[operand2, e, esize]; if unsigned then constant integer element1 = UInt(op1elt); constant integer element2 = UInt(op2elt); (Elem[result, e, esize], -) = UnsignedSatQ(element1 + element2, esize); else constant integer element1 = SInt(op1elt); constant integer element2 = SInt(op2elt); (Elem[result, e, esize], -) = SignedSatQ(element1 + element2, esize); Z[d, VL] = result;
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