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SMOV

Signed move vector element to general-purpose register

This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Advanced SIMD class

(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Q001110000imm5001011RnRd
opimm4

32-bit encoding

(Q == 0)

SMOV <Wd>, <Vn>.<Ts>[<index>]

64-bit encoding

(Q == 1)

SMOV <Xd>, <Vn>.<Ts>[<index>]

Decode (all encodings)

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); if imm5 == 'xx000' then EndOfDecode(Decode_UNDEF); constant integer size = LowestSetBitNZ(imm5<2:0>); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer esize = 8 << size; constant integer datasize = 32 << UInt(Q); if datasize <= esize then EndOfDecode(Decode_UNDEF); constant integer index = UInt(imm5<4:size+1>); constant integer idxdsize = 64 << UInt(imm5<4>);

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Ts>

For the "32-bit" variant: is an element size specifier, encoded in imm5:

imm5 <Ts>
xxx00 RESERVED
xxxx1 B
xxx10 H

For the "64-bit" variant: is an element size specifier, encoded in imm5:

imm5 <Ts>
xx000 RESERVED
xxxx1 B
xxx10 H
xx100 S
<index>

For the "32-bit" variant: is the element index encoded in imm5:

imm5 <index>
xxx00 RESERVED
xxxx1 UInt(imm5<4:1>)
xxx10 UInt(imm5<4:2>)

For the "64-bit" variant: is the element index encoded in imm5:

imm5 <index>
xx000 RESERVED
xxxx1 UInt(imm5<4:1>)
xxx10 UInt(imm5<4:2>)
xx100 UInt(imm5<4:3>)
<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

Operation

if index == 0 then AArch64.CheckFPEnabled(); else AArch64.CheckFPAdvSIMDEnabled(); constant bits(idxdsize) operand = V[n, idxdsize]; X[d, datasize] = SignExtend(Elem[operand, index, esize], datasize);

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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