SHA1 hash update (choose)
SHA1 hash update (choose).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rm | 0 | 0 | 0 | 0 | 0 | 0 | Rn | Rd | ||||||||||||
| size | opcode | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SHA1) then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm);
| <Qd> |
Is the 128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field. |
| <Sn> |
Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rn" field. |
| <Vm> |
Is the name of the third SIMD&FP source register, encoded in the "Rm" field. |
AArch64.CheckFPAdvSIMDEnabled(); bits(128) x = V[d, 128]; bits(32) y = V[n, 32]; // Note: 32 not 128 bits wide constant bits(128) w = V[m, 128]; for e = 0 to 3 constant bits(32) t = SHAchoose(x<63:32>, x<95:64>, x<127:96>); y = y + ROL(x<31:0>, 5) + t + Elem[w, e, 32]; x<63:32> = ROL(x<63:32>, 30); constant bits(160) yx = ROL(y:x, 32); (y, x) = (yx<159:128>, yx<127:0>); V[d, 128] = x;