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SEL

Multi-vector conditional select

This instruction selects consecutive elements from the two or four first source vectors where vector select predicate elements are true, and places them in the corresponding elements of the two or four destination vectors. Where vector select predicate elements are false, the corresponding consecutive elements are selected from the two or four second source vectors and placed in the remaining elements of the destination vectors.

It has encodings from 2 classes: Two registers and Four registers

Two registers class

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001size1Zm0100PNvZn0Zd0

Encoding

SEL { <Zd1>.<T>-<Zd2>.<T> }, <PNv>, { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }

Decode

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn::'0'); let m : integer = UInt(Zm::'0'); let d : integer = UInt(Zd::'0'); let v : integer = UInt('1'::PNv); let nreg : integer{} = 2;

Four registers class

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
11000001size1Zm01100PNvZn00Zd00

Encoding

SEL { <Zd1>.<T>-<Zd4>.<T> }, <PNv>, { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }

Decode

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn::'00'); let m : integer = UInt(Zm::'00'); let d : integer = UInt(Zd::'00'); let v : integer = UInt('1'::PNv); let nreg : integer{} = 4;

Assembler Symbols

<Zd1>

For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<PNv>

Is the name of the vector select predicate register PN8-PN15, with predicate-as-counter encoding, encoded as "PNv" plus 8.

<Zn1>

For the "Two registers" variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.

<Zn2>

Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zm1>

For the "Two registers" variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 2.

For the "Four registers" variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 4.

<Zm2>

Is the name of the second scalable vector register of the second source multi-vector group, encoded as "Zm" times 2 plus 1.

<Zd4>

Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

<Zn4>

Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.

<Zm4>

Is the name of the fourth scalable vector register of the second source multi-vector group, encoded as "Zm" times 4 plus 3.

Operation

CheckStreamingSVEEnabled(); let VL : integer{} = CurrentVL(); let PL : integer{} = VL DIV 8; let elements : integer = VL DIV esize; var results : array[[4]] of bits(VL); let pred : bits(PL) = P{}(v); let mask : bits(PL * nreg) = CounterToPredicate{}(pred[15:0]); for r = 0 to nreg-1 do let operand1 : bits(VL) = Z{}(n+r); let operand2 : bits(VL) = Z{}(m+r); for e = 0 to elements-1 do if ActivePredicateElement{PL*nreg}(mask, r * elements + e, esize) then results[[r]][e*:esize] = operand1[e*:esize]; else results[[r]][e*:esize] = operand2[e*:esize]; end; end; end; for r = 0 to nreg-1 do Z{VL}(d+r) = results[[r]]; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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