SCVTFLT

Signed integer convert to floating-point (top, unpredicated)

This instruction converts each odd-numbered signed integer element of the source vector to floating-point, and places the results in the overlapping double-width elements of the destination vector.

This instruction is unpredicated.

SVE2 class

(FEAT_SVE2p3 || FEAT_SME2p3)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	size		0	0	1	1	0	0	0	0	1	1	1	0	Zn					Zd
																					U

Encoding

SCVTFLT <Zd>.<T>, <Zn>.<Tb>

Decode

if !IsFeatureImplemented(FEAT_SVE2p3) && !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); end; if size == '00' then EndOfDecode(Decode_UNDEF); end; let esize : integer{} = 8 << UInt(size); let n : integer = UInt(Zn); let d : integer = UInt(Zd); let unsigned : boolean = FALSE; let rounding : FPRounding = FPRoundingMode(FPCR());

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size	<T>
00	RESERVED
01	H
10	S
11	D

<Zn>	Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size:

size	<Tb>
00	RESERVED
01	B
10	H
11	S

Operation

CheckSVEEnabled(); let VL : integer{} = CurrentVL(); let elements : integer = VL DIV esize; let operand : bits(VL) = Z{}(n); var result : bits(VL); for e = 0 to elements-1 do let element : bits(esize DIV 2) = operand[(2*e + 1)*:(esize DIV 2)]; result[e*:esize] = FixedToFP{esize, esize DIV 2}(element, 0, unsigned, FPCR(), rounding); end; Z{VL}(d) = result;