Rounding shift right narrow by immediate (bottom)
This instruction shifts each unsigned integer value in the source vector elements right by an immediate value, and places the rounded results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | tszh | 1 | tszl | imm3 | 0 | 0 | 0 | 1 | 1 | 0 | Zn | Zd | |||||||||||
| op | U | R | T | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then EndOfDecode(Decode_UNDEF); constant bits(3) tsize = tszh:tszl; if tsize == '000' then EndOfDecode(Decode_UNDEF); constant integer esize = 8 << HighestSetBitNZ(tsize); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer shift = (2 * esize) - UInt(tsize:imm3);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
| <Tb> |
Is the size specifier,
encoded in
|
| <const> |
Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3". |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV (2 * esize); constant bits(VL) operand = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(2*esize) element = Elem[operand, e, 2*esize]; constant integer res = (UInt(element) + (1 << (shift-1))) >> shift; Elem[result, 2*e + 0, esize] = res<esize-1:0>; Elem[result, 2*e + 1, esize] = Zeros(esize); Z[d, VL] = result;
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
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