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RCWSSWP, RCWSSWPA, RCWSSWPAL, RCWSSWPL

Read check write software swap doubleword in memory

This instruction atomically loads a 64-bit doubleword from a memory location, and conditionally stores the value held in a register back to the same memory location. Storing back to memory is conditional on RCW Checks and RCWS Checks. The value initially loaded from memory is returned in the destination register. If the RCW Checks fail or the RCWS Checks fail, the architecture permits writing the value read from the location to memory. If the write is performed, the read and the write occur atomically such that no other modification of the memory location can take place between the read and the write. This instruction updates the condition flags based on the result of the RCW Checks and RCWS Checks.

Note

This instruction is for performing atomic updates of translation table entries and not for general use.

Integer class

(FEAT_THE)

313029282726252423222120191817161514131211109876543210
01111000AR1Rs101000RnRt
SVRo3opc

RCWSSWP encoding

(A == 0 && R == 0)

RCWSSWP <Xs>, <Xt>, [<Xn|SP>]

RCWSSWPA encoding

(A == 1 && R == 0)

RCWSSWPA <Xs>, <Xt>, [<Xn|SP>]

RCWSSWPAL encoding

(A == 1 && R == 1)

RCWSSWPAL <Xs>, <Xt>, [<Xn|SP>]

RCWSSWPL encoding

(A == 0 && R == 1)

RCWSSWPL <Xs>, <Xt>, [<Xn|SP>]

Decode (all encodings)

if !IsFeatureImplemented(FEAT_THE) then EndOfDecode(Decode_UNDEF); end; let s : integer{} = UInt(Rs); let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let soft : boolean = TRUE; let acquire : boolean = A == '1' && t != 31; let release : boolean = R == '1'; let tagchecked : boolean = n != 31;

Assembler Symbols

<Xs>

Is the 64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.

<Xt>

Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

if IsD128Enabled(PSTATE.EL) then Undefined(); end; var address : bits(64); let newdata : bits(64) = X{}(s); var readdata : bits(64); var nzcv : bits(4); let accdesc : AccessDescriptor = CreateAccDescRCW(MemAtomicOp_SWP, soft, acquire, release, tagchecked, t, s); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let compdata : bits(64) = ARBITRARY : bits(64); // Irrelevant when not executing CAS (nzcv, readdata) = MemAtomicRCW{64}(address, compdata, newdata, accdesc); PSTATE.[N,Z,C,V] = nzcv; X{64}(t) = readdata; // Return the old value when t!=31

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