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PRFM (literal)

Prefetch memory (literal)

This instruction signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as making the cache line containing the specified address available at the level of cache specified by the instruction.

The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory.

For information about addressing modes, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
11011000imm19Rt
opcVR

Encoding

PRFM (<prfop>|#<imm5>), <label>

Decode for this encoding

constant integer t = UInt(Rt); constant bits(64) offset = SignExtend(imm19:'00', 64);

Assembler Symbols

<prfop>

Is the prefetch operation, defined as <type><target><policy>.

<type> is one of:

PLD
Prefetch for load, encoded in the "Rt<4:3>" field as 0b00.
PLI
Preload instructions, encoded in the "Rt<4:3>" field as 0b01.
PST
Prefetch for store, encoded in the "Rt<4:3>" field as 0b10.

<target> is one of:

L1
Level 1 cache, encoded in the "Rt<2:1>" field as 0b00.
L2
Level 2 cache, encoded in the "Rt<2:1>" field as 0b01.
L3
Level 3 cache, encoded in the "Rt<2:1>" field as 0b10.
SLC
When FEAT_PRFMSLC is implemented, system level cache, encoded in the "Rt<2:1>" field as 0b11.

<policy> is one of:

KEEP
Retained or temporal prefetch, allocated in the cache normally. Encoded in the "Rt<0>" field as 0.
STRM
Streaming or non-temporal prefetch, for data that is used only once. Encoded in the "Rt<0>" field as 1.

For more information on these prefetch operations, see Prefetch memory.

For other encodings of the "Rt" field, use <imm5>.

Rt <prfop> Architectural Feature
00000 PLDL1KEEP -
00001 PLDL1STRM -
00010 PLDL2KEEP -
00011 PLDL2STRM -
00100 PLDL3KEEP -
00101 PLDL3STRM -
00110 PLDSLCKEEP FEAT_PRFMSLC
00111 PLDSLCSTRM FEAT_PRFMSLC
01000 PLIL1KEEP -
01001 PLIL1STRM -
01010 PLIL2KEEP -
01011 PLIL2STRM -
01100 PLIL3KEEP -
01101 PLIL3STRM -
01110 PLISLCKEEP FEAT_PRFMSLC
01111 PLISLCSTRM FEAT_PRFMSLC
10000 PSTL1KEEP -
10001 PSTL1STRM -
10010 PSTL2KEEP -
10011 PSTL2STRM -
10100 PSTL3KEEP -
10101 PSTL3STRM -
10110 PSTSLCKEEP FEAT_PRFMSLC
10111 PSTSLCSTRM FEAT_PRFMSLC
<imm5>

Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.

This syntax is only for encodings that are not accessible using <prfop>.

<label>

Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

Operation

constant bits(64) address = PC64 + offset; Prefetch(address, t<4:0>);