Prefetch memory (immediate)
This instruction provides a hint to the memory system.
The PRFM IR variant of this instruction signals to the memory system that the thread of execution on the current PE will read a location that might not yet have been updated with the value the thread needs, and that the memory system should optimize for low-latency delivery of that value when the write by the other observer does occur.
The other variants of this instruction signal to the memory system that memory accesses to a location are likely to occur soon. The memory system can respond by taking actions that are expected to speed up the memory access when it does occur, such as making the cache line containing the specified address available at the level of cache specified by the instruction.
For all variants of this instruction, the address for memory accesses is calculated from a base register value and an immediate offset.
The <prfop> operand specifies the prefetch hint as follows:
The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory.
For information about addressing modes, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | imm12 | Rn | Rt | |||||||||||||||||||
| size | VR | opc | |||||||||||||||||||||||||||||
let offset : bits(64) = LSL(ZeroExtend{64}(imm12), 3); let n : integer = UInt(Rn); let t : integer = UInt(Rt); let nontemporal : boolean = FALSE; let tagchecked : boolean = FALSE;
| <imm5> |
Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field. This syntax is only for encodings that are not accessible using <prfop>. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <pimm> |
Is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8. |
var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_PREFETCH, nontemporal, privileged, tagchecked, t); if n == 31 then address = SP{64}(); else address = X{64}(n); end; address = AddressAdd(address, offset, accdesc); let supports_ir : boolean = IsFeatureImplemented(FEAT_PCDPHINT); Prefetch(address, t[4:0], supports_ir);
Version 2026.06 — Copyright © 2010-2026 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.