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PMOV (to predicate)

Move predicate from vector

This instruction copies a packed bitmap, where bit value 0b1 represents TRUE and bit value 0b0 represents FALSE, from a portion of the source vector register to elements of the destination SVE predicate register.

Because the number of bits in an SVE predicate element scales with the vector element size, the behavior varies according to the specified element size.

The portion index is optional, defaulting to 0 if omitted.

It has encodings from 4 classes: Byte , Doubleword , Halfword and Word

Byte class

(FEAT_SVE2p1 || FEAT_SME2p1)

313029282726252423222120191817161514131211109876543210
0000010100101010001110Zn0Pd
opcopc2

Encoding

PMOV <Pd>.B, <Zn>

Decode

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant integer esize = 8; constant integer imm = 0;

Doubleword class

(FEAT_SVE2p1 || FEAT_SME2p1)

313029282726252423222120191817161514131211109876543210
000001011i3h101i3l0001110Zn0Pd

Encoding

PMOV <Pd>.D, <Zn>{[<imm>]}

Decode

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant integer esize = 64; constant integer imm = UInt(i3h:i3l);

Halfword class

(FEAT_SVE2p1 || FEAT_SME2p1)

313029282726252423222120191817161514131211109876543210
00000101001011i10001110Zn0Pd
opc

Encoding

PMOV <Pd>.H, <Zn>{[<imm>]}

Decode

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant integer esize = 16; constant integer imm = UInt(i1);

Word class

(FEAT_SVE2p1 || FEAT_SME2p1)

313029282726252423222120191817161514131211109876543210
0000010101101i20001110Zn0Pd
opc

Encoding

PMOV <Pd>.S, <Zn>{[<imm>]}

Decode

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then EndOfDecode(Decode_UNDEF); constant integer n = UInt(Zn); constant integer d = UInt(Pd); constant integer esize = 32; constant integer imm = UInt(i2);

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<imm>

For the "Doubleword" variant: is the optional portion index, in the range 0 to 7, defaulting to 0, encoded in the "i3h:i3l" fields.

For the "Halfword" variant: is the optional portion index, in the range 0 to 1, defaulting to 0, encoded in the "i1" field.

For the "Word" variant: is the optional portion index, in the range 0 to 3, defaulting to 0, encoded in the "i2" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(VL) operand = Z[n, VL]; bits(PL) result; constant integer psize = esize DIV 8; for e = 0 to elements-1 Elem[result, e, psize] = ZeroExtend(operand<(elements * imm) + e>, psize); P[d, PL] = result;

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