NOTS

Bitwise invert predicate, setting the condition flags

This instruction performs a bitwise invert on each active element of the source predicate, and places the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. This instruction sets the First (N), None (Z), and !Last (C) condition flags based on the predicate result, and sets the V flag to zero.

This is an alias of EORS. This means:

The encodings in this description are named to match the encodings of EORS.
The description of EORS gives the operational pseudocode, any constrained unpredictable behavior, and any operational information for this instruction.

Setting the condition flags class

(FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	1	0	1	0	0	Pm				0	1	Pg				1	Pn				0	Pd
								op	S													o2					o3

Encoding

NOTS <Pd>.B, <Pg>/Z, <Pn>.B

is equivalent to

EORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pg>.B

and is the preferred disassembly when Pm == Pg.

Assembler Symbols

<Pd>	Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Pg>	Is the name of the governing scalable predicate register, encoded in the "Pg" field.

<Pn>	Is the name of the source scalable predicate register, encoded in the "Pn" field.

Operation

The description of EORS gives the operational pseudocode for this instruction.

Operational Information

The description of EORS gives the operational information for this instruction.

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31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	1	0	1	0	0	Pm				0	1	Pg				1	Pn				0	Pd
								op	S													o2					o3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	1	0	1	0	0	Pm				0	1	Pg				1	Pn				0	Pd
								op	S													o2					o3