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NOT (predicate)

Bitwise invert predicate

This instruction performs a bitwise invert on each active element of the source predicate, and places the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. This instruction does not set the condition flags.

This is an alias of EOR (predicates). This means:

Not setting the condition flags class

(FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
001001010000Pm01Pg1Pn0Pd
opSo2o3

Encoding

NOT <Pd>.B, <Pg>/Z, <Pn>.B

is equivalent to

EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pg>.B

and is the preferred disassembly when Pm == Pg.

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<Pg>

Is the name of the governing scalable predicate register, encoded in the "Pg" field.

<Pn>

Is the name of the source scalable predicate register, encoded in the "Pn" field.

Operation

The description of EOR (predicates) gives the operational pseudocode for this instruction.

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