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MOVI

Move immediate (vector)

This instruction places an immediate constant into every vector element of the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Advanced SIMD class

(FEAT_AdvSIMD)

313029282726252423222120191817161514131211109876543210
0Qop0111100000abccmode01defghRd
o2

8-bit encoding

(op == 0 && cmode == 1110)

MOVI <Vd>.<T>, #<imm8>{, LSL #0}

16-bit shifted immediate encoding

(op == 0 && cmode == 10x0)

MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>}

32-bit shifted immediate encoding

(op == 0 && cmode == 0xx0)

MOVI <Vd>.<T>, #<imm8>{, LSL #<amount>}

32-bit shifting ones encoding

(op == 0 && cmode == 110x)

MOVI <Vd>.<T>, #<imm8>, MSL #<amount>

64-bit scalar encoding

(Q == 0 && op == 1 && cmode == 1110)

MOVI <Dd>, #<imm>

64-bit vector encoding

(Q == 1 && op == 1 && cmode == 1110)

MOVI <Vd>.2D, #<imm>

Decode (all encodings)

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end; let rd : integer = UInt(Rd); let datasize : integer{} = 64 << UInt(Q); let imm64 : bits(64) = AdvSIMDExpandImm(op, cmode, a::b::c::d::e::f::g::h); let imm : bits(datasize) = Replicate{}(imm64);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

For the "8-bit" variant: is an arrangement specifier, encoded in Q:

Q <T>
0 8B
1 16B

For the "16-bit shifted immediate" variant: is an arrangement specifier, encoded in Q:

Q <T>
0 4H
1 8H

For the "32-bit shifted immediate" and "32-bit shifting ones" variants: is an arrangement specifier, encoded in Q:

Q <T>
0 2S
1 4S
<imm8>

Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".

<amount>

For the "16-bit shifted immediate" variant: is the shift amount encoded in cmode[1]:

cmode[1] <amount>
0 0
1 8
defaulting to 0 if LSL is omitted.

For the "32-bit shifted immediate" variant: is the shift amount encoded in cmode[2:1]:

cmode[2:1] <amount>
00 0
01 8
10 16
11 24
defaulting to 0 if LSL is omitted.

For the "32-bit shifting ones" variant: is the shift amount encoded in cmode[0]:

cmode[0] <amount>
0 8
1 16
<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<imm>

Is a 64-bit immediate 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh', encoded in "a:b:c:d:e:f:g:h".

Operation

AArch64_CheckFPAdvSIMDEnabled(); V{datasize}(rd) = imm;

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