Move vector register (unpredicated)
This instruction copies the contents of the source vector register to the destination vector register. This instruction is unpredicated.
This is an alias of ORR (vectors, unpredicated). This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Zm | 0 | 0 | 1 | 1 | 0 | 0 | Zn | Zd | ||||||||||||
| opc | |||||||||||||||||||||||||||||||
is equivalent to
and is the preferred disassembly when Zn == Zm.
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
The description of ORR (vectors, unpredicated) gives the operational pseudocode for this instruction.
The description of ORR (vectors, unpredicated) gives the operational information for this instruction.
Version 2025.09 — Copyright © 2010-2025 Arm Limited or its affiliates.
This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.