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MOV (tile to vector, four registers)

Move ZA four-slice operand to Z four-vector operand

This instruction operates on a horizontal or vertical ZA four-slice operand within a ZA tile of the specified element size.

The first slice of the four-slice operand is selected by rounding down the sum of the slice index register and the immediate offset to the nearest lower multiple of 4, modulo the number of slices in the tile.

The immediate offset is a multiple of 4 in the range 0 to the number of elements in a 128-bit vector segment minus 4.

This instruction is unpredicated.

This is an alias of MOVA (tile to vector, four registers). This means:

It has encodings from 4 classes: 8-bit , 16-bit , 32-bit and 64-bit

8-bit class

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000000000110VRs001000off2Zd00
size

8-bit encoding

MOV { <Zd1>.B-<Zd4>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs4>]

is equivalent to

MOVA { <Zd1>.B-<Zd4>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs4>]

and is always the preferred disassembly.

16-bit class

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000001000110VRs001000ZAno1Zd00
size

16-bit encoding

MOV { <Zd1>.H-<Zd4>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs4>]

is equivalent to

MOVA { <Zd1>.H-<Zd4>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs4>]

and is always the preferred disassembly.

32-bit class

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000010000110VRs001000ZAnZd00
size

32-bit encoding

MOV { <Zd1>.S-<Zd4>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs4>]

is equivalent to

MOVA { <Zd1>.S-<Zd4>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs4>]

and is always the preferred disassembly.

64-bit class

(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1100000011000110VRs00100ZAnZd00
size

64-bit encoding

MOV { <Zd1>.D-<Zd4>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs4>]

is equivalent to

MOVA { <Zd1>.D-<Zd4>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs4>]

and is always the preferred disassembly.

Assembler Symbols

<Zd1>

Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<Zd4>

Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

<HV>

Is the horizontal or vertical slice indicator, encoded in V:

V <HV>
0 H
1 V
<Ws>

Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.

<offs1>

For the "8-bit" variant: is the first slice index offset, encoded as "off2" field times 4.

For the "16-bit" variant: is the first slice index offset, encoded as "o1" field times 4.

For the "32-bit" and "64-bit" variants: is the first slice index offset, with implicit value 0.

<offs4>

For the "8-bit" variant: is the fourth slice index offset, encoded as "off2" field times 4 plus 3.

For the "16-bit" variant: is the fourth slice index offset, encoded as "o1" field times 4 plus 3.

For the "32-bit" and "64-bit" variants: is the fourth slice index offset, with implicit value 3.

<ZAn>

For the "16-bit" variant: is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAn" field.

For the "32-bit" variant: is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAn" field.

For the "64-bit" variant: is the name of the ZA tile ZA0-ZA7 to be accessed, encoded in the "ZAn" field.

Operation

The description of MOVA (tile to vector, four registers) gives the operational pseudocode for this instruction.

Operational Information

The description of MOVA (tile to vector, four registers) gives the operational information for this instruction.

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