MOV (SIMD&FP scalar, unpredicated)

Move indexed element or SIMD&FP scalar to vector (unpredicated)

This instruction unconditionally broadcasts the SIMD&FP scalar into each element of the destination vector. This instruction is unpredicated.

This is an alias of DUP (indexed). This means:

The encodings in this description are named to match the encodings of DUP (indexed).
The description of DUP (indexed) gives the operational pseudocode, any constrained unpredictable behavior, and any operational information for this instruction.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1	imm2		1	tsz					0	0	1	0	0	0	Zn					Zd

is equivalent to

and is the preferred disassembly when BitCount(imm2:tsz) == 1.

is equivalent to

and is the preferred disassembly when BitCount(imm2:tsz) > 1.

Assembler Symbols

<Zd>	Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in tsz:

<V>

Is a width specifier, encoded in tsz:

<n>	Is the number [0-31] of the source SIMD&FP register, encoded in the "Zn" field.

<Zn>	Is the name of the source scalable vector register, encoded in the "Zn" field.

<imm>

Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".

The description of DUP (indexed) gives the operational pseudocode for this instruction.

The description of DUP (indexed) gives the operational information for this instruction.

This site is provided as a community resource and is NOT affiliated with nor endorsed by Arm Limited.