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LUTI6 (8-bit)

Lookup table read with 6-bit indices (8-bit)

This instruction copies indexed 8-bit elements from the low 256 bits of the two table vectors to the destination vector using packed 6-bit indices from the bottom three quarters of the source vector.

This instruction is unpredicated.

This instruction requires that the Effective SVE vector length is at least 256 bits.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

SVE2 class

(FEAT_SVE2p3)

313029282726252423222120191817161514131211109876543210
01000101001Zm101011ZnZd

Encoding

LUTI6 <Zd>.B, { <Zn1>.B, <Zn2>.B }, <Zm>

Decode

if !IsFeatureImplemented(FEAT_SVE2p3) then EndOfDecode(Decode_UNDEF); if MaxImplementedAnyVL() < 256 then EndOfDecode(Decode_UNDEF); constant integer isize = 6; constant integer esize = 8; constant integer m = UInt(Zm); constant integer n = UInt(Zn); constant integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn1>

Is the name of the first table vector register, encoded as "Zn".

<Zn2>

Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32.

<Zm>

Is the name of the source scalable vector register, encoded in the "Zm" field.

Operation

CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < 256 then EndOfDecode(Decode_UNDEF); constant integer elements = VL DIV esize; constant bits(VL) indexes = Z[m, VL]; // Only bottom 3/4 used constant bits(512) table = Z[(n+1) MOD 32, VL]<255:0> : Z[n+0, VL]<255:0>; bits(VL) result; for e = 0 to elements-1 constant integer index = UInt(Elem[indexes, e, isize]); constant bits(esize) res = Elem[table, index, esize]; Elem[result, e, esize] = res; Z[d, VL] = result;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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