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LUTI6 (table, four registers, 8-bit)

Lookup table read with 6-bit indices (8-bit)

This instruction copies indexed 8-bit elements from ZT0 to four destination vectors using packed 6-bit indices in the three source vectors. This instruction is unpredicated.

It has encodings from 2 classes: Consecutive and Strided

Consecutive class

(FEAT_SME2p3)

313029282726252423222120191817161514131211109876543210
1100000010001010000000Zn00Zd00
sizeopc

Encoding

LUTI6 { <Zd1>.B-<Zd4>.B }, ZT0, { <Zn1>-<Zn3> }

Decode

if !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); constant integer esize = 8; constant integer isize = 6; constant integer n = UInt('00':Zn); constant integer dstride = 1; constant integer d = UInt(Zd:'00');

Strided class

(FEAT_SME2p3)

313029282726252423222120191817161514131211109876543210
1100000010011010000000Zn00D00Zd
sizeopc

Encoding

LUTI6 { <Zd1>.B, <Zd2>.B, <Zd3>.B, <Zd4>.B }, ZT0, { <Zn1>-<Zn3> }

Decode

if !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); constant integer esize = 8; constant integer isize = 6; constant integer n = UInt('00':Zn); constant integer dstride = 4; constant integer d = UInt(D:'00':Zd);

Assembler Symbols

<Zd1>

For the "Consecutive" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

For the "Strided" variant: is the name of the first scalable vector register Z0-Z3 or Z16-Z19 of the destination multi-vector group, encoded as "D:'00':Zd".

<Zd4>

For the "Consecutive" variant: is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

For the "Strided" variant: is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 of the destination multi-vector group, encoded as "D:'11':Zd".

<Zn1>

Is the name of the first scalable vector register of the source multi-vector group Z0-Z7, encoded in the "Zn" field.

<Zn3>

Is the name of the third scalable vector register of the source multi-vector group Z2-Z9, encoded as "Zn" plus 2.

<Zd2>

Is the name of the second scalable vector register Z4-Z7 or Z20-Z23 of the destination multi-vector group, encoded as "D:'01':Zd".

<Zd3>

Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 of the destination multi-vector group, encoded as "D:'10':Zd".

Operation

CheckStreamingSVEEnabled(); CheckSMEZT0Enabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(3*VL) indexes = Z[n+2, VL] : Z[n+1, VL] : Z[n+0, VL]; integer dst = d; constant bits(512) table = ZT0[512]; for r = 0 to 3 constant integer base = r * elements; bits(VL) result; for e = 0 to elements-1 constant integer index = UInt(Elem[indexes, base+e, isize]); Elem[result, e, esize] = Elem[table, index, esize]; Z[dst, VL] = result; dst = dst + dstride;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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