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LUTI6 (vector, 16-bit)

Lookup table read with 6-bit indices (16-bit)

This instruction copies indexed 16-bit elements from the low 512 bits of the two table vectors to four destination vectors using packed 6-bit indices in the low or high one and a half vector segment of the two source vectors. The source vectors segment consumed in order to fill the destination vectors is selected by the source vector segment index. This instruction is unpredicated. This instruction requires that the Effective SVE vector length is at least 512 bits.

It has encodings from 2 classes: Consecutive and Strided

Consecutive class

(FEAT_SME2p3)

313029282726252423222120191817161514131211109876543210
110000010i11Zm111101ZnZd00

Encoding

LUTI6 { <Zd1>.H-<Zd4>.H }, { <Zn1>.H, <Zn2>.H }, { <Zm1>-<Zm2> }[<index>]

Decode

if !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); if MaxImplementedAnyVL() < 512 then EndOfDecode(Decode_UNDEF); constant integer esize = 16; constant integer isize = 6; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer dstride = 1; constant integer d = UInt(Zd:'00'); constant integer select = UInt(i1);

Strided class

(FEAT_SME2p3)

313029282726252423222120191817161514131211109876543210
110000010i11Zm111111ZnD00Zd

Encoding

LUTI6 { <Zd1>.H, <Zd2>.H, <Zd3>.H, <Zd4>.H }, { <Zn1>.H, <Zn2>.H }, { <Zm1>-<Zm2> }[<index>]

Decode

if !IsFeatureImplemented(FEAT_SME2p3) then EndOfDecode(Decode_UNDEF); if MaxImplementedAnyVL() < 512 then EndOfDecode(Decode_UNDEF); constant integer esize = 16; constant integer isize = 6; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer dstride = 4; constant integer d = UInt(D:'00':Zd); constant integer select = UInt(i1);

Assembler Symbols

<Zd1>

For the "Consecutive" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

For the "Strided" variant: is the name of the first scalable vector register Z0-Z3 or Z16-Z19 of the destination multi-vector group, encoded as "D:'00':Zd".

<Zd4>

For the "Consecutive" variant: is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

For the "Strided" variant: is the name of the fourth scalable vector register Z12-Z15 or Z28-Z31 of the destination multi-vector group, encoded as "D:'11':Zd".

<Zn1>

Is the name of the first table vector register, encoded as "Zn".

<Zn2>

Is the name of the second table vector register, encoded as "Zn" plus 1 modulo 32.

<Zm1>

Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zm".

<Zm2>

Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zm" plus 1 modulo 32.

<index>

Is the vector segment index, in the range 0 to 1, encoded in the "i1" field.

<Zd2>

Is the name of the second scalable vector register Z4-Z7 or Z20-Z23 of the destination multi-vector group, encoded as "D:'01':Zd".

<Zd3>

Is the name of the third scalable vector register Z8-Z11 or Z24-Z27 of the destination multi-vector group, encoded as "D:'10':Zd".

Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < 512 then EndOfDecode(Decode_UNDEF); constant integer elements = VL DIV esize; constant bits(2*VL) operand = Z[(m+1) MOD 32, VL] : Z[m+0, VL]; constant integer idxsize = VL + (VL DIV 2); constant integer idxpos = if select == 1 then (VL DIV 2) else 0; constant bits(idxsize) indexes = operand<idxpos+:idxsize>; constant bits(1024) table = Z[(n+1) MOD 32, VL]<511:0> : Z[n+0, VL]<511:0>; integer dst = d; bits(VL) result; for r = 0 to 3 constant integer base = r * elements; for e = 0 to elements-1 constant integer index = UInt(Elem[indexes, base+e, isize]); Elem[result, e, esize] = Elem[table, index, esize]; Z[dst, VL] = result; dst = dst + dstride;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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