LDUR (SIMD&FP)

Load SIMD&FP register (unscaled offset)

This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Unscaled offset class

(FEAT_FP)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
size		1	1	1	1	0	0	x	1	0	imm9									0	0	Rn					Rt
					VR			opc

8-bit encoding

(size == 00 && opc == 01)

LDUR <Bt>, [<Xn|SP>{, #<simm>}]

16-bit encoding

(size == 01 && opc == 01)

LDUR <Ht>, [<Xn|SP>{, #<simm>}]

32-bit encoding

(size == 10 && opc == 01)

LDUR <St>, [<Xn|SP>{, #<simm>}]

64-bit encoding

(size == 11 && opc == 01)

LDUR <Dt>, [<Xn|SP>{, #<simm>}]

128-bit encoding

(size == 00 && opc == 11)

LDUR <Qt>, [<Xn|SP>{, #<simm>}]

Decode (all encodings)

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if opc[1] == '1' && size != '00' then EndOfDecode(Decode_UNDEF); end; let scale : integer{} = if opc[1] == '1' then 4 else UInt(size); let offset : bits(64) = SignExtend{}(imm9);

Assembler Symbols

<Bt>	Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

<Ht>	Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<St>	Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Dt>	Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Qt>	Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

Shared Decode

let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let datasize : integer{} = 8 << scale; let nontemporal : boolean = FALSE; let tagchecked : boolean = n != 31;

Operation

AArch64_CheckFPEnabled(); var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked, privileged); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; address = AddressAdd(address, offset, accdesc); V{datasize}(t) = Mem{datasize}(address, accdesc);

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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