LDRSB (register)

Load register signed byte (register)

This instruction calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it, and writes it to a register. For information about addressing modes, see Load/Store addressing modes.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	1	1	0	0	0	1	x	1	Rm					option			S	1	0	Rn					Rt
size					VR			opc

32-bit with extended register offset encoding

(opc == 11 && option != 011)

LDRSB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]

32-bit with shifted register offset encoding

(opc == 11 && option == 011)

LDRSB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]

64-bit with extended register offset encoding

(opc == 10 && option != 011)

LDRSB <Xt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]

64-bit with shifted register offset encoding

(opc == 10 && option == 011)

LDRSB <Xt>, [<Xn|SP>, <Xm>{, LSL <amount>}]

Decode (all encodings)

if option[1] == '0' then EndOfDecode(Decode_UNDEF); end; // sub-word index let extend_type : ExtendType = DecodeRegExtend(option); let shift : integer{} = 0;

Assembler Symbols

<Wt>	Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Wm>	When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.

<Xm>	When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.

Is the index extend specifier, encoded in option:

option	<extend>
010	UXTW
110	SXTW
111	SXTX

Is the index shift amount, it must be #0, encoded in "S" as 0 if omitted, or as 1 if present.

<Xt>	Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

Shared Decode

let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let regsize : integer{} = 64 >> UInt(opc[0]); let nontemporal : boolean = FALSE; let tagchecked : boolean = TRUE;

Operation

let offset : bits(64) = ExtendReg{}(m, extend_type, shift); var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged, tagchecked, t); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; address = AddressAdd(address, offset, accdesc); let data : bits(8) = Mem{8}(address, accdesc); X{regsize}(t) = SignExtend{regsize}(data);

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

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